The CGS13 uses an 8-stage digital shift register as a memory element. Each clock pulse, the remembered level (logic 0 or logic 1) is moved into the next stage "bucket brigade" fashion, and the new value stored in the first memory cell. The result is a random level (on or off) at a predetermined time at the first output, plus time delayed versions of previous levels across the remaining outputs.

CGS13 Datasheet and Build Guide