The Sample & Hold used in the ASM-2 is based on a fairly straight-forward and common design that uses an FET to store the `sampled' voltage on to a low-leakage capacitor.
The S&H sample
clock may be derived from an external source or taken from the S&H
low-frequency oscillator dedicated to the S&H module.
The S&H will accept an input signal up to +/-10V.
An LED is included on the board to provide a visual status of the S&H trigger signal.
© Copyright 2000. All rights reserved. Revised: February 27, 2015