This module is the combination of a quad comparator "voting system" and memory cell (flip-flop). It can be built in many ways to suit the builder's needs. For example, if the memory cell functions are not required, they can be omitted. Alternatively, the panel presence of the comparators can be greatly reduced if the memory cell is the primary interest.
The comparator "voting" circuits can be used as OR, AND or 2 of 3, 2 of 4, 3 of 4 etc. type gates, depending on construction. Both positive responding and negative responding inputs are available.
Master AND and OR outputs monitor the four voting circuits. The four voting circuits are used to drive the flip-flop memory cell, providing SET, RESET, CLOCK and DATA inputs.
The purpose of the module is to allow the combination of various gate events and CVs to generate responses, rhythms, etc.