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The ASM-2 Sample & Hold Module How VCO VCA VCF ADSR S & H LFO GLIDE PSU PCB About HOW Setup Schematic Wiring

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The Sample & Hold (S&H) module consists of three circuits:-

1. clock circuit,
2. trigger conditioning circuit, and
3. sample & hold circuit

1) The clock circuit is a very simple square-wave oscillator built around a single CMOS inverter gate (U903A) the output of which is buffered by U903B. This buffered LFO clock signal is then connected to the trigger conditionig circuit. As an option, the user can take this signal via a panel switch/socket and provide and external trigger signal for the S&H module.

2) The clock signal, be it from the clock circuit or from an external source, is then fed through a level shifter to provide a 0-15V signal. This conversion, of course, is not required when using the clock circuit but as this converter also provides a visual indication of the trigger signal, it is left in circuit. The trigger signal is buffered by U903F and U903E and then split in to two paths. One path goes through U903D and provides a buffered copy of the trigger signal for external use (SH-GATE). The second path goes through C903, R906 and D904 to generate a negative-going pulse which is buffered by U903C. This signal now goes through U901B which is configured as a comparator and provides a-15V to +15V output swing (S&H-TRIGGER) in response to the (conditioned) clock signal.

3) R901 and C901form a pre-sample-and-hold circuit which is buffered by U901A. Whilst S&H-TRIGGER is at +15V, the `pre-sampled' signal at the output of U901A is fed to the S&H capacitor C902. When S&H-TRIGGER goes to -15V the FET is turned off and provides a very high impedance path to C902. This `sampled' voltage is buffered by U902 to provide the Sample & Hold output.

The choice of the type of capacitor used for C902 will have a profound affect on the performance of the Sample & Hold module and should be a very-low-leakage type. The high leakage characteristic of electrolytics and the transient behavior of ceramics rule them out completely in this application. The best choice is probably polypropylene, and then polystyrene or Mylar. Polycarbonate is much inferior to all of these. The greatest problem (after leakage, which should be practically zero) is dielectric hysteresis in which the voltage changes on charge and discharge are not the same. There is also dielectric absorption, where there is a "memory" of past states. A capacitor freshly discharged may acquire a small voltage as time goes by. All of these phenomena are the result of the complexity of dielectric structure and behavior.